NXP Semiconductors /MIMXRT1021 /LPSPI1 /CFGR0

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Interpret as CFGR0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)HREN 0 (DISABLED)HRPOL 0 (HREQPIN)HRSEL 0 (DISABLED)CIRFIFO 0 (STORED)RDMO

HRPOL=DISABLED, HRSEL=HREQPIN, HREN=DISABLED, RDMO=STORED, CIRFIFO=DISABLED

Description

Configuration Register 0

Fields

HREN

Host Request Enable

0 (DISABLED): Host request is disabled

1 (ENABLED): Host request is enabled

HRPOL

Host Request Polarity

0 (DISABLED): LPSPI_HREQ pin is active high provided PCSPOL[1] is clear

1 (ENABLED): LPSPI_HREQ pin is active low provided PCSPOL[1] is clear

HRSEL

Host Request Select

0 (HREQPIN): Host request input is the LPSPI_HREQ pin

1 (INPUT_TRIGGER): Host request input is the input trigger

CIRFIFO

Circular FIFO Enable

0 (DISABLED): Circular FIFO is disabled

1 (ENABLED): Circular FIFO is enabled

RDMO

Receive Data Match Only

0 (STORED): Received data is stored in the receive FIFO as in normal operations

1 (DISCARDED): Received data is discarded unless the Data Match Flag (DMF) is set

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